1. Field of the Invention
The present invention relates to a data memory system, and for example, the invention is applied to a high-reliability data memory system provided with a semiconductor memory device, in which a defective bit can be relieved even if the defective bit is generated.
2. Description of the Related Art
In the data memory system provided with the semiconductor memory device, there has been developed a nonvolatile semiconductor memory (EEPROM), in which charges injected into a charge accumulation layer from a channel through an insulator by a tunnel current are used for digital bit information storage and a change in conductance of MOSFET is measured according to a charge amount to read the information. Among others, in a NAND type EEPROM (NAND type flash memory) in which plural memory cells are connected in series or in parallel to form a memory cell block, the number of selection transistor gates can significantly be decreased compared with the number of memory cells, and higher density can be achieved. In a structure of the NAND type EEPROM, a well in which the memory cells are formed is commonly used, erasing is collectively performed to a page formed by the plural memory cells, and programming is performed to individual memory cell, so that the higher density can be achieved. In the nonvolatile memory, unlike DRAM, data can be read plural times without destroying the data.
However, when a capacitive coupling of adjacent cells is increased with the further advance of miniaturization and high density, a threshold voltage is changed by the charge amounts of charge accumulation layers of the adjacent cells, thereby lowering a threshold voltage margin between information bits. Particularly, in the NAND type flash memory, program disturbance in which the bit to be kept in the erasing state is changed to the programming bit is generated even in collectively-erased erasing bits by a data pattern during the programming, which results in a problem that the threshold voltage margin is further lowered.
In order to solve the wrong bit problem, for example, Jpn. Pat. Appl. KOKAI Publication No. 2005-243183, applied by the inventors, discloses a method for performing error correction with ECC (Error Correcting Code). However, there is no characteristic, effective ECC producing method against a problem that the erasing threshold or programming threshold voltage is raised by the capacitive coupling because the adjacent memory cell is changed from the erasing threshold to the programming threshold, and a problem that the generation of the wrong programming is increased by a pattern of the adjacent memory cell.
More specifically, in the case where a BCH (Bose-Chaudhuri-Hocquenghem) code is used as ECC, a code length n is fixed to 2m−1 (m is a natural number) as a t-fold error correcting code, and the number of corresponding information bits k0 is restricted to k0=2m−1−mt. In the case where an RS (Reed-Solomon) code is used as ECC, one byte is set at m bits as the t-fold error correcting code, the code length n is 2m−1 (byte), and the number of corresponding information bits k1 is restricted to k1=2m−1−2t. Thus, the conventional BCH code and the RS code have a small degree of freedom due to the restrictions of the code length and the like, in order to obtain shorter ECC code.
As described above, the conventional BCH code producing method and RS code producing method are not a strong error correcting method against a particular series of code patterns such as “010”, but are an error correcting method against a random single bit or a random certain number of bytes.
Therefore, the conventional BCH code producing method or RS code producing method cannot solve the particular problem that the erasing threshold voltage or programming threshold voltage is raised by the capacitive coupling because the adjacent memory cell is changed from the erasing threshold voltage to the programming threshold voltage, and the problem that the generation of the wrong programming is increased by the pattern of the adjacent memory cell. Conventionally an effective coding method is not disclosed even if the BCH code and the RS code are combined.
Thus, the conventional data memory system cannot deal with the particular-pattern problem in which the programming disturbance is generated by the pattern of the adjacent memory cell in changing the erasing threshold voltage or programming threshold voltage due to the capacitive coupling, but the data memory system can deal with the error correction of the random single bit or a random certain number of bytes. As a result, the strong error correction cannot be performed to the particular series of code patterns such as “010”.